Closed-loop timing authority
External TESTSET timing follows virtual BO/contact/wire/BI behavior with independent clock domains rather than direct access to relay private trip state.
Current research contributions
Shipped mechanisms with traceable implementation and tests.
Causal relay acquisition
Instantaneous terminal samples, signed clipping/quantization, configured delay, settled pre-fault history, and a causal rolling measurement connect source behavior to protection timing.
Operator evidence semantics
Generic ANY PICKUP, TESTSET BI2, operated-element pickup/P→T, relay trip request, TESTSET BI1, frozen capture, and reset/re-arm remain distinct.
Process-bus trust
Identity, mapping/scaling, continuity, quality, complete windows, and permission gates provide a reproducible trust-before-trip model.
Transformer Differential
87T/87T-HS/REF, security, synchronized two-sided internal injection, and paired-SV external evaluation provide a current transformer research surface.
AVR / OLTC and MMS
The virtual plant, 17-position OLTC, authority/interlocks, reports, and modeled MMS controls support repeatable control-system experiments without physical authority.
Technical notes
Read the implementation assumptions before interpreting results.
AN-01
Signal processing
Nominal-frequency complete-window phasor estimation assumptions, evidence, and limitations.
AN-02Continuity and recovery
smpCnt, duplicate/out-of-order behavior, stale windows, reset/recovery, and trust transitions.
Directional protection
Polarizing quantities, directional decisions, and validation boundaries for 67 functions.
Validation
Connect public claims to deterministic scenarios.
Validation matrix
Foundational process-bus scenarios plus beta.6 closed-loop metrology regressions and current release gates.
Machine-readable scenarios
Versioned scenario IDs with source/test references for reproducible public traceability.
Related work
Standards, established engineering concepts, and external technical context without unsupported superiority claims.
Current scientific boundaries
Beta.6 is stronger software evidence, not a hardware metrology claim.
- The TESTSET and relay timing profile is deterministic behavioral software, not traceably calibrated equipment.
- The default relay front end is generic, not a reverse-engineered manufacturer-specific analog/ADC/protection pipeline.
- Process-bus phasor estimation retains its documented nominal-frequency/window assumptions.
- Transformer and AVR models are vendor-neutral laboratory behavior, not conformance profiles.
- Windows live performance depends on host scheduling, adapters, drivers, and publishers.
Future evidence tracks
Measure the missing physics and implementation details.
Device-specific relay/test-set profiles
Measure anti-alias response, externally observable ADC behavior, channel skew, burden, BI thresholds, contact statistics, and timing uncertainty.
Estimator characterization
Expand frequency, harmonic/interharmonic, noise, decaying-DC, and CT-saturation characterization before broader accuracy claims.
HIL and deterministic hosts
Use calibrated independent timestamps and defined scheduling contracts to compare software timing with controlled hardware and deployment environments.
Claim boundary
Research pages do not create certification.
ARVREL does not claim calibrated relay-test-set accuracy, manufacturer-specific relay equivalence, IEC 61850 conformance, IEC 60255 type testing, protection-grade hard-real-time operation, commissioning acceptance, or field-control authority.