Closed-loop feeder TESTSET timing
1 µs metrology clock, 10 kHz BI sampling, causal relay front end, external BI1 trip authority, explicit ANY-PICKUP semantics, frozen capture, and one-click re-arm.
Maturity labels
Every capability must carry an evidence state.
| Label | Meaning | Required evidence |
|---|---|---|
| Implemented | Available in the selected public beta. | Source, deterministic tests, documentation, release packaging, explicit boundary. |
| Validated baseline | Core operate/restrain or positive/negative behavior has stable regression coverage. | Stable scenarios, CI traceability, evidence output, repeatable expected result. |
| Research track | Design/evidence plan exists but the stronger claim is not shipped. | Entry criteria, instrumentation, test matrix, failure/safety model. |
| Deferred | Useful but outside current release priorities. | Explicit dependency and public reason. |
| Out of scope | Not part of the product claim. | Explicit non-claim preventing unsafe interpretation. |
Shipped beta.6 baseline
These are no longer roadmap-only items.
IEC 61850 SV and feeder protection
Live Npcap, PCAP/PCAPNG replay, SCL-assisted identity/mapping/scaling/trust, 50/51/67/27/59/59N, settings identity, and evidence.
Trust-before-trip
Measurement/pickup/trip permissions plus duplicate/out-of-order rejection and continuity/recovery evidence.
Transformer Differential
87T, 87T-HS, REF HV/LV, H2/H5 security, CT/vector compensation, deterministic 10-scenario self-test, synchronized two-sided internal injection, and paired-SV evaluation.
AVR / OLTC and MMS
Simulated transformer plant, 17-position OLTC, modeled authority/interlocks, MMS browse/read, DataSets, reports, GI/integrity, and virtual SBO/SBOw controls.
Operational equipment authority
No physical trip contact, operational GOOSE, OLTC motor command, autonomous switching, primary-equipment control, or commissioning authority.
Research track A
Measured device-specific relay and test-set fidelity.
Beta.6 has a deterministic generic behavioral profile. The next fidelity step requires measurements against real equipment rather than more guessed constants.
Entry criteria
- Named hardware and firmware/revision under authorized laboratory access
- Calibrated independent timing and waveform instrumentation
- Repeatable source/load/reference setup
- Measurement uncertainty recorded separately from model fitting
Exit criteria for a device-specific profile
- Measured anti-alias/input transfer response
- ADC range/topology or externally observable equivalent behavior
- Channel skew and input burden characterization
- Binary-input electrical thresholds and timing
- Relay output/contact operate/release statistics
- Repeatable residual timing/error envelope across representative tests
Until complete: keep the beta.6 CMC-style TESTSET and numerical-relay profile labeled behavioral, generic, and non-calibrated.
Research track B
Signal-estimator robustness and characterization.
Expand beyond the current nominal-frequency one-cycle baseline before any broader accuracy claim.
Planned characterization
- 45–55 Hz and 55–65 Hz frequency sweeps
- Harmonic, interharmonic, noise, and quantization fixtures
- Decaying-DC and CT-saturation waveforms
- Window/estimator comparisons
Protection impact
- Operate and restrain sensitivity
- Directional quantity stability
- Pickup timing sensitivity
- CPU/allocation cost and deterministic replay evidence
Current claim: the process-bus estimator remains a nominal-frequency, complete one-cycle, mean-removed single-bin DFT; it is not a general FFT analyzer or calibrated PMU.
Research track C
Transformer-protection fidelity beyond the current generic model.
87T/REF is already shipped. Future work should deepen validation rather than describe the function itself as planned.
More vector groups
Add compensation only with explicit phasor fixtures, through-load stability, internal-fault dependability, and documented zero-sequence treatment.
Measured CT behavior
Use real or validated CT saturation/remanence waveforms and independent neutral-current scenarios to extend security evidence.
Cross-device paired SV
Expand interoperability across diverse publishers, synchronization conditions, stream restarts, and realistic network disturbances.
Research track D
Deployment-oriented virtualization and timing benchmarks.
The Windows desktop remains a laboratory product. Deterministic-host research must define a timing contract instead of inheriting one from faster hardware or a virtual machine label.
Candidate environment
- Linux real-time or another deterministic host profile
- CPU affinity/isolation and bounded allocation
- Explicit scheduling policy
- Independent ingress/output timestamp instrumentation
- Fault containment and restart behavior
Required metrics
- Ingress-to-measurement latency
- Measurement-to-pickup latency
- Pickup-to-operation latency
- Worst-case and percentile jitter
- Load/packet-loss/contention sensitivity
- Recovery and failover time
No inherited claim: CPU affinity, real-time Linux, or virtualization alone does not make ARVREL protection-grade hard real time.
Research track E
Independent hardware-in-the-loop comparison.
Software fixtures
Continue stable scenario IDs, source-to-test traceability, and CI regression.
Controlled publishers and captures
Use sanitized PCAP and controlled SV/MMS clients for continuity, identity, scaling, timing, transformer, and AVR interoperability stress.
Calibrated HIL
Use calibrated sources and independent timestamps to compare measured quantities, relay operation, TESTSET timing, restraint, reset, and recovery.
Certification boundary: successful internal HIL remains engineering validation. It is not automatically IEC 60255 type testing or IEC 61850 conformance certification.
Deferred functions
Visible backlog without false availability.
46, 47, 49, 81U/O, 32, 37, 50BF, 79, 25, 86, 74TCS, 60, negative-sequence 67N polarization, and memory polarization remain deferred unless a future release explicitly promotes them.