Signed terminal samples
Virtual wiring produces instantaneous current/voltage samples at the relay boundary.
Closed-loop feeder path
The external virtual-I/O chain owns TESTSET timing.
01TESTSET T0 + instantaneous source
02Virtual analog wiring
03Relay ADC/front-end model
04Causal measurement + protection
05Relay BO contact behavior
06Virtual binary wiring
07Independent TESTSET BI acceptance
Authority invariant: internal
TripLatched can request BO1 but cannot become a TESTSET result directly. Accepted wired BI1 owns external trip timing and optional auto-stop.Clock domains
Metrology, relay processing, and rendering are different clocks.
| Domain | beta.6 reference behavior | Authority |
|---|---|---|
| TESTSET metrology | Monotonic integer µs, 1 µs resolution | T0 and timing arithmetic |
| TESTSET BI | 10 kHz / 100 µs, 0.5 ms deglitch, 0 ms debounce holdoff | Accepted external pickup/trip edges |
| Relay acquisition | 4 kHz / 250 µs | Terminal sampling and protection progression |
| WPF | Slower presentation cadence | Display only |
Relay front end
Protection sees causal terminal samples, not source-side phasors.
Input model
Signed clipping, 16-bit-equivalent quantization, 20 A/300 V RMS behavioral full scale, and 1.5 ms input/filter delay.
Rolling measurement
One nominal 50 Hz causal DFT begins from settled pre-fault history rather than an artificial empty window.
Timing semantics
Generic pickup is not the same as operated-element pickup.
RELAY ANY PU / BI2
BO2 is generic ANY PICKUP. Another enabled element can assert it before the element that later operates.
Operated-element P→T
Element timing is correlated to the element in the authoritative operation record. A representable 60 ms 50P definite delay is exactly 60.000 ms in the reference engine.
Relay trip / BI1
The live trip request drives BO1; BI1 acceptance is the external TESTSET result.
Reset and frozen evidence
Reset settles modeled feedback without erasing the completed run.
After BI1 auto-stop the source is OFF while the trip capture stays frozen. One reset transaction advances acquisition until stale pickup releases, clears the relay once, then waits for no pickup, BO1/BO2 LOW, and BI1/BI2 LOW before showing READY TO RE-ARM. The source is not restarted and completed timing evidence is retained.
Other product paths
Process bus, Transformer Differential, and AVR/MMS use separate shared runtimes.
Process bus
Live/Replay Ethernet frames flow through ARIEC61850 decode, identity, mapping/scaling, continuity/quality, complete windows, trust, and feeder/transformer runtime.
Transformer Differential
Internal synchronized HV/LV/NGR injection or paired external SV feeds the same transformer protection runtime for 87T, 87T-HS, and REF evidence.
AVR / OLTC + MMS
The simulated plant and controller expose browse/read, DataSets, reports, and modeled controls. Accepted commands terminate inside the virtual process.
Architecture boundary
Behavioral models do not imply hardware equivalence.
Exact commercial relay anti-alias filters, ADC topology, burdens, channel skew, electrical BI thresholds, statistical contact behavior, and calibrated timing uncertainty are not claimed by beta.6.