Clock domains
Compare 1 µs TESTSET metrology, 10 kHz BI sampling, 4 kHz relay processing, and non-authoritative WPF rendering cadence.
Closed-loop experiments
Study why external timing differs from internal relay state.
Pickup attribution
Show how generic ANY PICKUP/BI2 can precede the pickup of the element that ultimately operates.
Open-wire experiment
Disconnect BO1→BI1 and demonstrate internal relay trip without an external TESTSET trip result.
Causal acquisition
Explore settled pre-fault history, instantaneous samples, clipping/quantization, input delay, rolling DFT response, and protection timing.
Reset/re-arm lifecycle
Observe frozen capture after BI1 auto-stop, then one deterministic reset transaction to READY TO RE-ARM while completed evidence is retained.
Process-bus research
Make provenance and trust part of the experiment.
- Replay authorized PCAP/PCAPNG fixtures for repeatability.
- Vary identity, mapping, scaling, quality, freshness, gaps, duplicate/out-of-order frames, and recovery.
- Record when data remains visible but
AllowsMeasurement,AllowsPickup, orAllowsTripchanges. - Preserve scenario ID, source/test reference, settings fingerprint, and expected outcome.
Transformer Differential
87T/REF is a shipped laboratory path, not future-only work.
Self-test baseline
Use the deterministic 10-scenario suite as a reproducible packaged-core reference.
Two-sided injection
Study through-load compensation, internal faults, independent neutral/NGR inputs, REF HV/LV, and H2/H5 security.
Paired external SV
Investigate synchronization, stream identity, continuity, mapping/scaling, and trust across two transformer-side publishers.
AVR / OLTC
Study control authority without field authority.
Control dynamics
Use the simulated transformer and 17-position OLTC to examine deadband, tap motion, AUTO/MANUAL, LOCAL/REMOTE, and interlocks.
IEC 61850 MMS
Evaluate browse/read, DataSets, event/integrity reporting, modeled SBO/SBOw controls, and virtual settings while commands terminate inside the simulator.
Research method
Make each claim traceable and falsifiable.
- State the question and expected result before running the scenario.
- Record ARVREL version, settings, source/run identity, topology, and relevant clock/timing profile.
- Use deterministic internal fixtures or redistributable sanitized captures when possible.
- Record positive and negative cases, not only successful operation.
- Keep observations separate from extrapolations to real hardware.
- Publish limitations and unresolved uncertainty with the result.
Future research
The next frontier is measured fidelity, not relabeling shipped features.
Device-specific anti-alias response, ADC behavior, input burden, channel skew, binary-input thresholds, contact statistics, hardware-calibrated timing uncertainty, broader estimator characterization, deterministic-host benchmarking, and independent HIL comparison require new measured evidence.